1. Field of the Invention
The present invention relates to a structure of a semiconductor device and a method for manufacturing the same, and more particularly, to a structure of a semiconductor device including gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low parasitic capacitance and a halo ion-implanted region in which a short channel effect can be effectively suppressed, and a method for manufacturing the same capable of performing high angle ion implantation without extending gate-to-gate space.
2. Description of the Related Art
In semiconductor devices employing a MOS transistor, critical dimension (CD) of the gate electrode has many effects on the properties of the MOS transistor. As semiconductor devices become highly integrated, the CD of the gate electrode becomes smaller. As a result, a method for forming a shallow junction is used so as to improve a short channel effect caused by scale down of the MOS transistor. However, this has limitations in reducing resistance of a source/drain extension region. As an alternative to this, halo ion implantation has been suggested. However, as the CD of the gate electrode becomes much smaller, the concentration of halo ion implantation becomes higher, resulting in an increase in junction capacitance and junction leakage current, and a decrease in on-current. High angle ion implantation has been suggested to solve these problems.
High angle ion implantation is a method for selectively implanting impurity ions into the sides of source/drain extension regions by using a high angle during ion implantation to form a halo ion-implanted region, and effectively prevents a short channel effect even though impurity ions with low concentration are implanted into the sides of the source/drain extension regions. When the concentration of the impurities in the halo ion-implanted region is reduced, a body effect is reduced, thereby increasing on-current and reducing off-current. Further, the high angle halo ion implantation causes a decrease in junction capacitance and a decrease in variation in gate length. However, as semiconductor devices become highly integrated, due to limitations in gate-to-gate space, halo ion implantation having more than a predetermined angle is impossible, and thus, the advantages of the high angle halo ion implantation cannot be realized. That is, as previously described, the high angle halo ion implantation is essentially used to manufacture a high performance transistor. However, due to adjacent gate electrodes, a shadowing effect occurs during ion implantation, and thus, the high angle halo ion implantation cannot be performed. In order to solve the problem, the interval between gate electrodes should be extended, or the height of the gate electrode should be reduced. However, extending intervals between gate electrodes results in an increase in chip size and runs counter to high integration. Further, reducing the height of the gate electrode does not provide a sufficient height margin for the formation of silicate required to reduce resistance, increasing the possibility that silicate on a gate may attack a gate oxide layer or an active region, and thus, sufficient gate electrode height for a subsequent chemical mechanical polishing (CMP) process cannot be obtained.
FIG. 1 is a sectional view illustrating effects of the height of a gate electrode and a gate-to-gate space on an ion implantation angle.
Referring to FIG. 1, when the interval between gate electrodes is a, the height of the gate electrode is b, and the angle between a normal to the surface of the semiconductor substrate 10 and the path of the impurity ions is xcex8, a sufficient ratio of a: b is required in order to employ high angle halo ion implantation. To achieve this, the interval a between gate electrodes should be sufficiently extended, or the height b of the gate electrode should be sufficiently reduced. However, reducing the height b of the gate results in the margin of the height of a gate being insufficient for the formation of silicide required to reduce resistance, and the gate oxide layer 12 or the active region may be attacked by silicide on the gate, and a gate electrode of sufficient height for a subsequent CMP process cannot be obtained. Extending the interval a between gate electrodes results in loss in a design rule, and thus the size of the chip becomes larger.
This runs counter to high integration in the semiconductor manufacturing process.
To solve the above problem, it is a first object of the present invention to provide a structure of a semiconductor device including gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low parasitic capacitance and a halo ion-implanted region in which a short channel effect can be effectively suppressed.
It is a second object of the present invention to provide a method for manufacturing the same capable of performing high angle ion implantation without extending gate-to-gate space.
In accordance with the invention, there is provided a semiconductor device. The semiconductor device includes a first ion-implanted region formed in a semiconductor substrate, a second ion-implanted region formed at both sides of the first ion-implanted region, a halo ion-implanted region adjacent to the second ion-implanted region opposite the first ion-implanted region, a gate oxide layer formed on the semiconductor substrate, a first gate electrode formed on the gate oxide layer, a silicon nitride (Si3N4) layer formed on the semiconductor substrate and along side-walls of the gate oxide layer and the first gate electrode, an oxide layer adjacent to the silicon nitride (Si3N4) layer, opposite the first gate electrode, a second gate electrode formed on the first gate electrode, the silicon nitride (Si3N4) layer, and the oxide layer, and first spacers formed on sidewalls of the second gate electrode and the oxide layer.
In one embodiment, gate electrodes comprised of the first gate electrode and the second gate electrode have a T-shaped structure in which the width of the second gate electrode is greater than that of the first gate electrode.
The silicon nitride (Si3N4) layer formed at both sides of the first gate electrode has an L-shaped or reverse L-shaped cross-section.
In one embodiment, the gate oxide layer is formed on the semiconductor substrate between the second ion-implanted regions.
The first ion-implanted region can be formed on the semiconductor substrate in a region wider than an interval between the first spacers.
An impurity in the halo ion-implanted region has a conductivity type opposite to that of the impurity in the first and second ion-implanted regions.
The concentration of impurity in the first ion-implanted region is higher than that of the second ion-implanted region.
It is preferable that the concentration of impurity in the first ion-implanted region be 3xc3x971015xcx9c7xc3x971015 cmxe2x88x922, and the concentration of impurity in the second ion-implanted region be 1xc3x971014xcx9c2xc3x971015 cmxe2x88x922.
It is also preferable that the concentration of an impurity in the halo ion-implanted region be 1xc3x971013xcx9c5xc3x971014 cmxe2x88x922.
It is also preferable that the first gate electrode be formed of polycrystalline silicon or silicon germanium (SiGe).
It is also preferable that the height of the first gate electrode be 500-1000 xc3x85.
It is also preferable that the second gate electrode is formed of polycrystalline silicon or silicon germanium (SiGe).
It is also preferable that the height of the second gate electrode be 300-1500 xc3x85.
It is also preferable that the silicon nitride (Si3N4) layer be formed to a thickness of 30-200 xc3x85.
The structure may further include a third ion-implanted region formed in the semiconductor substrate between the first spacers, and a second spacer formed at the sides of the first spacers.
In accordance with the invention, there is also provided a method for manufacturing a semiconductor device. In accordance with the method, a gate oxide layer and a first gate electrode are formed on a semiconductor substrate. A source/drain extension region is formed by implanting impurity ions into the semiconductor substrate. A halo ion-implanted region is formed at both sides of the source/drain extension region by implanting impurity ions at a predetermined angle between a normal to the semiconductor substrate, by using a high angle halo ion implantation method. A silicon nitride (Si3N4) layer is formed on the semiconductor substrate on which the halo ion-implanted region is formed. An oxide layer is formed on the semiconductor substrate on which the silicon nitride (Si3N4) layer is formed. The semiconductor substrate on which the oxide layer is formed is planarized by chemical mechanical polishing to expose the first gate electrode. A second gate electrode is formed on the first gate electrode using a selective epitaxial growth method. The oxide layer is etched back to expose the silicon nitride (Si3N4) layer using the second gate electrode as an etch mask. An insulating layer for forming spacers is deposited on the semiconductor substrate, and a first spacer is formed by anisotropic dry etching. A first deep source/drain region is formed by implanting impurity ions into the semiconductor substrate.
In one embodiment, the step of forming the first spacer is performed before the step of forming the first deep source/drain region, and after the step of etching back the oxide layer. After the step of forming the first deep source/drain region, an insulating layer for forming spacers is deposited on the semiconductor substrate and a second spacer is formed by anisotropic dry etching, and a second deep source/drain region is formed by implanting impurity ions into the semiconductor substrate. The step of forming the second spacer and the step of implanting impurity ions are repeated twice or more.
The step of forming the first deep source/drain region is performed before the step of forming the second spacer, and after the step of etching back the oxide layer. After the step of forming the second spacer, a second deep source/drain region is formed by implanting impurity ions into the semiconductor substrate, and an insulating layer for forming spacers is deposited on the semiconductor substrate and a second spacer is formed by anisotropic dry etching. The step of implanting impurity ions and the step of forming the second spacer are repeated twice or more.
Before the step of forming the gate oxide layer and the first gate electrode, a device isolation region is formed on the semiconductor substrate, and impurity ions are implanted into the semiconductor substrate to control a threshold voltage.
It is preferable that the angle between a normal to the semiconductor substrate and the direction of implantation of the impurity ions be 30-80xc2x0.
In one embodiment, the height of the first gate electrode is controlled such that the maximum angle between a normal to the semiconductor substrate and the direction of implantation of the impurity ions is 30-80xc2x0. It is preferable that the height of the first gate electrode be 500-1500 xc3x85.
It is also preferable that the first gate electrode be formed of polycrystalline silicon or silicon germanium (SiGe).
The impurity in the halo ion-implanted region has a type opposite to that of the impurity in the source/drain extension region.
The concentration of the impurity in the first deep source/drain region is higher than that of the source/drain extension region.
It is preferable that the concentration of the impurity in the source/drain extension region be 1xc3x971014xcx9c2xc3x971015 cmxe2x88x922.
It is also preferable that the concentration of the impurity in the halo ion-implanted region be 1xc3x971013xcx9c5xc3x971014 cmxe2x88x922.
It is also preferable that the concentration of the impurity in the first deep source/drain region be 3xc3x971015xcx9c7xc3x971015 cmxe2x88x922.
It is also preferable that the height of the second gate electrode be 300-1500 xc3x85. It is also preferable that the second gate electrode be formed of polycrystalline silicon or silicon germanium (SiGe).
It is also preferable that the silicon nitride (Si3N4) layer be formed to a thickness of 30-200 xc3x85.
It is also preferable that the oxide layer be formed of high temperature oxide (HTO), middle temperature oxide (MTO), or low temperature oxide (LTO), having a high etching selectivity to the silicon nitride (Si3N4) layer.
Gate electrodes comprised of the first gate electrode and the second gate electrode have a T-shaped structure in which the width of the second gate electrode is greater than that of the first gate electrode.